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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver
The MPC993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.
MPC993
* * * * * * *
Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control/Statis I/O 3.3V Operation 32-Lead LQFP Packaging 50ps Cycle-Cycle Jitter
FA SUFFIX 32-LEAD PLASTIC LQFP PACKAGE CASE 873A-02
The MPC993 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
PLL_En Clk_Selected Inp1bad Inp0bad Man_Override Alarm_Reset Sel_Clk CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR OR Qb0 Qb0 Qb1 Qb1 /2 PLL /4 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1
Dynamic Switch Logic
Figure 1. Block Diagram
03/01
(c) Motorola, Inc. 2001
1
REV 3
MPC993
VCC
24 Qa1 Qa1 Qa0 Qa0 VCC VCCA Man_Override PLL_En 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
VCC 17 16 15 14 VCC Inp0bad Inp1bad Clk_Selected GND Ext_FB Ext_FB GND 13 12 11 10 9 8 Min GNDA
Qb0
Qb0
Qb1
Qb1
Qb2 6 CLK1
MPC993
2
3
4
5
Alarm_Reset
CLK0
CLK0
Figure 2. 32-Lead Pinout (Top View)
3.3V PECL DC Characteristics (TA = -40C to 85C, VCC = 3.3V 5%)
Symbol VOH VOL VPP VCMR VOH VOL VIH VIL IIL IEE Parameter Output HIGH Voltage (LVPECL Outputs) (50W to VCC - 2.0V) Output LOW Voltage (LVPECL Outputs) (50W to VCC - 2.0V) Input HIGH Voltage (LVPECL Inputs) Input LOW Voltage (LVPECL Inputs) Output HIGH Voltage (LVCMOS Outputs) Output LOW Voltage (LVCMOS Outputs) Input HIGH Voltage (LVCMOS Inputs) Input LOW Voltage (LVCMOS Inputs) Input LOW Current Power Supply Current GNDA GND 0.5 15 80 20 180 2.0 Typ Max VCC - 0.80 VCC - 1.60 1.0 VCC - 0.6 Unit V V V V V 0.5 3.3 0.8 V V V A mA VCC - 1.025 VCC - 1.80 0.3 1.0 2.4
MOTOROLA
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Sel_Clk
CLK1
MR
Qb2 7
TIMING SOLUTIONS DL207 -- Rev 0
MPC993
3.3V PECL AC Characteristics (TA = -40C to 85C, VCC = 3.3V 5%) (Note 6.)
Symbol fVCO tpwi tpd tr/tf tskew pe per/cycle Propagation Delay (Note 1.) Output Rise/Fall Time Output Skew Maximum Phase Error Deviation Rate of Change of Periods 75MHz Output (Note 1., 3.) 150MHz Output (Note 1., 3.) 75MHz Output (Note 1., 4.) 150MHz Output (Note 1., 4.) 45 (Note 1.) 20 10 200 100 Within Bank All Outputs CLKn to Q (Bypass) CLKn to Ext_FB (Locked (Note 2.)) PLL VCO Lock Range Parameter (Note 5.) Min 200 25 1.7 -150 200 2.3 0 Typ Max 360 75 2.8 170 800 70 100 TBD (Note 3.) TBD (Note 4.) 50 25 400 200 55 20 10 Unit MHz % ns ps ps ps ps ps/ cycle
tpw tjitter tlock
Output Duty Cycle Cycle-to-Cycle Jitter, Standard Deviation (RMS) Maximum PLL Lock Time
% ps ms
1. Guaranteed, not production tested. 2. Static phase offset between the selected reference clock and the feedback signal. 3. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. (See Applications Information section on page 4 for more detail) 4. Specification holds for a clock switch between two signals no greater than out of phase. Delta period change per cycle is averaged over the clock switch excursion. 5. The PLL will be unstable using a output as the feedback. Either one of the outputs (Qa0 or Qa1) should be used as the feedback signal. 6. PECL output termination is 50 ohms to VCC - 2.0V.
B2
B4
PIN DESCRIPTIONS
Pin Name CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa0:1, Qa0:1 Qb0:2, Qb0:2 Inp0bad Inp1bad Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND I/O LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output LVCMOS Output LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply Pin Definition Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs Differential 2x output pairs Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted `0' if clock 0 is selected, `1' if clock 1 is selected `0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is "one-shotted" (50k pullup) `0' selects CLK0, `1' selects CLK1 (50k pulldown) `1' disables internal clock switch circuitry (50k pulldown) `0' bypasses selected input reference around the phase-locked loop (50k pullup) `0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k pullup) PLL power supply Digital power supply PLL ground Digital ground
TIMING SOLUTIONS DL207 -- Rev 0
3
MOTOROLA
MPC993
Applications Information
The MPC993 is a dual clock PLL with on-chip Intelligent Dynamic Clock Switch (IDCS) circuitry. Definitions primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or IDCS. (IDCS can override Sel_Clk). Status Functions Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. INP_BAD: Latched (H) when it's CLK is stuck (H) or (L) for at least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared (L) on assertion of Alarm_Reset. Control Functions Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one-shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. Man Override (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. The status function INP_BAD is active in Man Override (H) and (L). Man Override (L) (IDCS is enabled, PLL functions enhanced). The first CLK to fail will latch it's INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk). NOTE: If both CLKs are bad when Alarm_Reset is asserted, both INP_BADs will be latched (H) after one Ext_FB period and Clk_Selected will be latched (L) indicating CLK0 is the PLL reference signal. While neither INP_BAD is latched (H), the Clk_Selected can be freely changed with Sel_Clk. Whenever a CLK switch occurs, (manually or by IDCS), following the next negative edge of the newly selected PLL reference signal, the next positive edge pair of Ext_FB and the newly selected PLL reference signal will slew to alignment. To calculate the overall uncertainty between the input CLKs and the outputs from multiple MPC993's, the following procedure should be used. Assuming that the input CLKs to all MPC993's are exactly in phase, the total uncertainty will be the sum of the static phase offset, max I/O jitter, and output to output skew. During a dynamic switch, the output phase between two devices may be increased for a short period of time. If the two input CLKs are 400ps out of phase, a dynamic switch of an MPC993 will result in an instantaneous phase change of 400ps to the PLL reference signal without a corresponding change in the output phase (due to the limited response of the PLL). As a result, the I/O phase of a device, undergoing this switch, will initially be 400ps and diminish as the PLL slews to its new phase alignment. This transient timing issue should be considered when analyzing the overall skew budget of a system. Hot insertion and withdrawal In PECL applications, a powered up driver will experience a low impedance path through an MPC993 input to its powered down VCC pins. In this case, a 100 ohm series resistance should be used in front of the input pins to limit the driver current. The resistor will have minimal impact on the rise and fall times of the input signals. Acquiring Frequency Lock 1. While the MPC993 is receiving a valid CLK signal, assert Man_Override HIGH. 2. The PLL will phase and frequency lock within the specified lock time. 3. Apply a HIGH to LOW transition to Alarm_Reset to reset Input Bad flags. 4. De-assert Man_Override LOW to enable Intelligent Dynamic Clock Switch mode.
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TIMING SOLUTIONS DL207 -- Rev 0
MPC993
OUTLINE DIMENSIONS
FA SUFFIX PLASTIC LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS DL207 -- Rev 0
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
5
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z- MOTOROLA
MPC993
NOTES
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TIMING SOLUTIONS DL207 -- Rev 0
MPC993
NOTES
TIMING SOLUTIONS DL207 -- Rev 0
7
MOTOROLA
MPC993
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MOTOROLA
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TIMING SOLUTIONS MPC993/D DL207 -- Rev 0

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